/*
* Copyright (c) 2019 MediaTek Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/

#pragma once

/* DISP Mutex */
#define DISP_MUTEX_TOTAL      (12)
#define DISP_MUTEX_DDP_FIRST  (0)
#define DISP_MUTEX_DDP_LAST   (3)   /* modify from 4 to 3, cause 4 is used for OVL0/OVL1 SW trigger */
#define DISP_MUTEX_DDP_COUNT  (4)
#define DISP_MUTEX_MDP_FIRST  (5)
#define DISP_MUTEX_MDP_COUNT  (5)

/* DISP MODULE */
typedef enum {
    DISP_MODULE_OVL0 = 0,       /* must start from 0 */
    DISP_MODULE_OVL1,
    DISP_MODULE_OVL0_2L,
    DISP_MODULE_OVL1_2L,
    DISP_MODULE_OVL0_VIRTUAL,
    DISP_MODULE_OVL0_2L_VIRTUAL,
    DISP_MODULE_OVL1_2L_VIRTUAL,

    DISP_MODULE_RDMA0,
    DISP_MODULE_RDMA1,
    DISP_MODULE_RDMA2,
    DISP_MODULE_RDMA_VIRTUAL0,

    DISP_MODULE_WDMA0,
    DISP_MODULE_WDMA1,
    DISP_MODULE_WDMA_VIRTUAL0,
    DISP_MODULE_WDMA_VIRTUAL1,

    DISP_MODULE_COLOR0,
    DISP_MODULE_COLOR1,
    DISP_MODULE_CCORR0,
    DISP_MODULE_CCORR1,
    DISP_MODULE_AAL0,
    DISP_MODULE_AAL1,
    DISP_MODULE_GAMMA0,
    DISP_MODULE_GAMMA1,
    DISP_MODULE_OD,
    DISP_MODULE_DITHER0,
    DISP_MODULE_DITHER1,

    DISP_MODULE_PATH0,
    DISP_MODULE_PATH1,

    DISP_MODULE_UFOE,
    DISP_MODULE_DSC,
    DISP_MODULE_DSC_2ND,
    DISP_MODULE_SPLIT0,     /* 30 */
    DISP_MODULE_DSI0,
    DISP_MODULE_DSI1,
    DISP_MODULE_DSIDUAL,
    DISP_MODULE_PWM0,
    DISP_MODULE_PWM1,

    DISP_MODULE_CONFIG,
    DISP_MODULE_MUTEX,
    DISP_MODULE_SMI_COMMON,
    DISP_MODULE_SMI_LARB0,
    DISP_MODULE_SMI_LARB1,

    DISP_MODULE_MIPI0,
    DISP_MODULE_MIPI1,

    DISP_MODULE_RSZ0,
    DISP_MODULE_RSZ1,
    DISP_MODULE_DPI,
    DISP_MODULE_DBI,
    DISP_MODULE_DPI_VIRTUAL,
    DISP_MODULE_POSTMASK,
    DISP_MODULE_UNKNOWN,

    DISP_MODULE_NUM
} DISP_MODULE_ENUM;

enum dst_module_type {
    DST_MOD_REAL_TIME,
    DST_MOD_WDMA,
};

static inline int check_ddp_module(DISP_MODULE_ENUM module)
{
    return module < DISP_MODULE_UNKNOWN;
}

typedef enum {
    DISP_REG_CONFIG,
    DISP_REG_OVL0,
    DISP_REG_OVL1,
    DISP_REG_OVL0_2L,
    DISP_REG_OVL1_2L,
    DISP_REG_RDMA0,
    DISP_REG_RDMA1,
    DISP_REG_RDMA2,
    DISP_REG_WDMA0,
    DISP_REG_WDMA1,
    DISP_REG_COLOR0,
    DISP_REG_COLOR1,
    DISP_REG_CCORR0,
    DISP_REG_CCORR1,
    DISP_REG_AAL0,
    DISP_REG_AAL1,
    DISP_REG_GAMMA0,
    DISP_REG_GAMMA1,
    DISP_REG_OD,
    DISP_REG_DITHER0,
    DISP_REG_DITHER1,
    DISP_REG_UFOE,
    DISP_REG_DSC,
    DISP_REG_SPLIT0,
    DISP_REG_DSI0,
    DISP_REG_DSI1,
    DISP_REG_DPI0,
    DISP_REG_PWM,
    DISP_REG_MUTEX,
    DISP_REG_SMI_LARB0,
    DISP_REG_SMI_LARB1,
    DISP_REG_SMI_COMMON,
    DISP_REG_MIPI0,
    DISP_REG_MIPI1,
    DISP_REG_NUM
} DISP_REG_ENUM;

enum OVL_LAYER_SOURCE {
    OVL_LAYER_SOURCE_MEM = 0,
    OVL_LAYER_SOURCE_RESERVED = 1,
    OVL_LAYER_SOURCE_SCL = 2,
    OVL_LAYER_SOURCE_PQ = 3,
};

enum OVL_LAYER_SECURE_MODE {
    OVL_LAYER_NORMAL_BUFFER = 0,
    OVL_LAYER_SECURE_BUFFER = 1,
    OVL_LAYER_PROTECTED_BUFFER = 2
};

typedef enum {
    CMDQ_DISABLE = 0,
    CMDQ_ENABLE
} CMDQ_SWITCH;

typedef enum {
    CMDQ_WAIT_LCM_TE,
    CMDQ_BEFORE_STREAM_SOF,
    CMDQ_WAIT_STREAM_EOF_EVENT,
    CMDQ_CHECK_IDLE_AFTER_STREAM_EOF,
    CMDQ_AFTER_STREAM_EOF,
    CMDQ_ESD_CHECK_READ,
    CMDQ_ESD_CHECK_CMP,
    CMDQ_ESD_ALLC_SLOT,
    CMDQ_ESD_FREE_SLOT,
    CMDQ_STOP_VDO_MODE,
    CMDQ_START_VDO_MODE,
    CMDQ_DSI_RESET,
    CMDQ_AFTER_STREAM_SOF,
    CMDQ_DSI_LFR_MODE,
} CMDQ_STATE;

typedef enum {
    DDP_IRQ_LEVEL_ALL = 0,
    DDP_IRQ_LEVEL_NONE,
    DDP_IRQ_LEVEL_ERROR
} DDP_IRQ_LEVEL;

